`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2017/11/07 10:58:03
// Design Name: 
// Module Name: mips
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
import structs::*;

module mips(
	input wire clk,rst,
	output wire[31:0] pcF,
	input wire[31:0] instrF,
	output wire[31:0] aluoutM,writedataM,
	input wire[31:0] readdataM,
	output wire[3:0] datamemEna,
	output wire[31:0] debug_wb_pc,
	output wire[3:0] debug_wb_rf_wen,
	output [4 :0] debug_wb_rf_wnum,
	output [31:0] debug_wb_rf_wdata,
	output wire data_sram_en,inst_sram_en,
	input wire stallreg_from_if,stallreg_from_mem,
	input wire[5:0] ext_int
    );
	
	wire [5:0] opD,functD;
	wire regdstE,alusrcE,pcsrcD,memtoregE,memtoregM,memtoregW,
			regwriteE,regwriteM,regwriteW;
	wire [2:0] alucontrolE;
	wire flushE,equalD;
	
    controller_sign_out_t controllerout;
    datapath_sign_out_t datapathout;
    
    assign memwriteM = controllerout.memwriteM;
    assign aluoutM = datapathout.aluoutM;
    assign pcF = datapathout.pcF;
    assign writedataM = datapathout.writedataM;
    
	assign debug_wb_pc = datapathout.debugPCW;
	assign debug_wb_rf_wen = {4{controllerout.regwriteW & ~datapathout.stallW}};
	assign debug_wb_rf_wnum = datapathout.writeregW;
	assign debug_wb_rf_wdata = datapathout.resultW;

	assign data_sram_en = (controllerout.lordM !=3'b000 | controllerout.storeM !=3'b000) & ~datapathout.except_jumpM;
	assign inst_sram_en = ~datapathout.except_jumpM;

	controller c(
		clk,rst,
		datapathout,
		controllerout
		);
	datapath dp(
		clk,rst,
		datapathout,
		controllerout,
	    instrF,
		readdataM,
		stallreg_from_if,stallreg_from_mem,
		ext_int,
		datamemEna
	    );
	
endmodule
